1. Technical Field
This invention relates in general to integrated circuits and, more particularly, to transistor structures.
2. Description of the Related Art
The great majority of electronic circuits used today are fabricated using a CMOS (complementary metal oxide semiconductor) process. There are two types of CMOS devices, N-type devices (NMOS) and P-type (PMOS) devices. An N-type device is turned on or off by the movement of electrons through an n-type doped channel. A P-type device is turned on or off by the movement of holes (electron vacancies) through a p-type doped channel.
The speed of a CMOS circuit depends largely upon the speed of the CMOS transistors. There is always pressure to increase the speed of the transistors to increase the processing capacity of a circuit. While much of the increases in speed over the last decade have been the result of smaller channel sizes, further increases in speed by reducing feature size will be more and more difficult to obtain.
For many years, it has been known that applying stress to a semiconductor material can change the mobility of electrons or holes in the doped regions. The effect of stress is dependent upon the lattice structure of the semiconductor material, the orientation of the channels on the semiconductor material, the type of stress (i.e., tensile or compressive), and the direction of the stress.
In U.S. Ser. No. 09/727,296 (Pub. No. US 2002/0063292), which is incorporated by reference herein, a method of forming CMOS devices so that current flows along a <100> direction in {100} silicon while applying a tensile longitudinal stress to the CMOS device. According to this reference, this technique increases electron mobility in the NMOS devices, while have a negligible effect on the PMOS devices.
In general, even in the absence of any stress, NMOS devices are significantly faster than PMOS devices in a given processing technology. Therefore, a need has arisen for a process which increases the speed of PMOS devices.